|
|
Brevets de Rambus
Les ingénieurs de Rambus ont développé de nombreuses innovations ayant conduit à plus de 727 brevets délivrés aux États-Unis et dans le monde et plus de 499 brevets en instance, dans des domaines tels que les interfaces mémoires et logiques, l’architecture mémoire, les liaisons parallèle et série haut débit, et la conception de systèmes.
La liste des brevets américains délivrés à Rambus par le Bureau américain des brevets et des marques de commerce (USPTO) est disponible ici.
Dernière mise à jour le 12 Novembre 2008
Liste des brevets de Rambus délivrés aux États-Unis
| Numéro de brevet |
Titre |
| 7,450,629 |
Adjustable dual-band link |
| 7,450,535 |
Pulsed signaling multiplexer |
| 7,448,397 |
Apparatus for applying disparate etching solutions to interior and exterior surfaces |
| 7,444,577 |
Memory device testing to support address-differentiated refresh rates |
| 7,443,941 |
Method and system for phase offset cancellation in systems using multi-phase clocks |
| 7,439,789 |
Systems and methods for controlling termination resistance values for a plurality of communication channels |
| 7,439,760 |
Configurable on-die termination |
| 7,437,527 |
Memory device with delayed issuance of internal write command |
| 7,433,397 |
Partial response receiver with clock data recovery |
| 7,423,454 |
High speed signaling system with adaptive transmit pre-emphasis |
| 7,421,548 |
Memory system and method for two step memory write operations |
| 7,420,990 |
Adaptive-allocation of I/O bandwidth using a configurable interconnect topology |
| 7,420,874 |
Integrated circuit memory device, system and method having interleaved row and column control |
| 7,417,871 |
Memory module |
| 7,415,073 |
Communication channel calibration for drift conditions |
| 7,414,489 |
Phase controlled oscillator circuit with input signal coupler |
| 7,412,016 |
Data-level clock recovery |
| 7,408,995 |
High speed communication system with a feedback synchronization loop |
| 7,408,981 |
Methods and circuits for performing margining tests in the presence of a decision feedback equalizer |
| 7,408,378 |
Calibration methods and circuits for optimized on-die termination |
| 7,404,032 |
Configurable width buffered module having switch elements |
| 7,400,671 |
Periodic calibration for communication channels by drift tracking |
| 7,400,670 |
Periodic calibration for communication channels by drift tracking |
| 7,398,413 |
Memory device signaling system and method with independent timing calibration for parallel signal paths |
| 7,398,333 |
Integrated circuit input/output interface with empirically determined delay matching |
| 7,397,848 |
Partial response receiver |
| 7,397,725 |
Single-clock, strobeless signaling system |
| 7,392,492 |
Multi-format consistency checking tool |
| 7,389,194 |
Driver calibration methods and circuits |
| 7,380,092 |
Memory device and system having a variable depth write buffer and preload method |
| 7,370,152 |
Memory controller with prefetching capability |
| 7,369,444 |
Early read after write operation memory device, system and method |
| 7,368,961 |
Clock distribution network supporting low-power mode |
| 7,366,275 |
Output calibrator with dynamic precision |
| 7,365,581 |
Regulated adaptive-bandwidth PLL/DLL using self-biasing current from a VCO/VCDL |
| 7,363,422 |
Configurable width buffered module |
| 7,362,800 |
Auto-configured equalizer |
| 7,362,626 |
Asynchronous, high-bandwidth memory component using calibrated timing elements |
| 7,362,130 |
Method and device for transmission with reduced crosstalk |
| 7,360,187 |
Mixed mode verifier |
| 7,360,127 |
Method and apparatus for evaluating and optimizing a signaling system |
| 7,360,050 |
Integrated circuit memory device having delayed write capability |
| 7,356,639 |
Configurable width buffered module having a bypass circuit |
| 7,353,357 |
Apparatus and method for pipelined memory operations |
| 7,352,234 |
Current control technique |
| 7,349,510 |
Apparatus for data recovery in a synchronous chip-to-chip system |
| 7,349,484 |
Adjustable dual-band link |
| 7,349,279 |
Memory Device Having a Configurable Oscillator for Refresh Operation |
| 7,348,811 |
Equalizing transceiver with reduced parasitic capacitance |
| 7,346,819 |
Through-core self-test with multiple loopbacks |
| 7,337,294 |
Method and apparatus for adjusting the performance of a synchronous memory system |
| 7,336,749 |
Statistical margin test methods and circuits |
| 7331006 |
Multiple Sweep Point Testing of Circuit Devices |
| 7330953 |
Memory System Having Delayed Write Timing |
| 7330952 |
Integrated Circuit Memory Device Having Delayed Write Timing Based on Read Response Time |
| 7330951 |
Apparatus and Method for Pipelined Memory Operations |
| 7321524 |
Memory Controller With Staggered Request Signal Output |
| 7320082 |
Power Control System for Synchronous Memory Device |
| 7320047 |
System Having a Controller Device, a Buffer Device and a Plurality of Memory Devices |
| 7319345 |
Wide-Range Multi-Phase Clock Generator |
| 7315929 |
Memory Device |
| 7313639 |
Memory System and Device With Serialized Data Transfer |
| 7308065 |
Delay Locked Loop Circuitry for Clock Delay Adjustment |
| 7308058 |
Transparent Multi-Mode PAM Interface |
| 7308048 |
System and Method for Selecting Optimal Data Transistion Types for Clock and Data Recovery |
| 7308044 |
Technique for Receiving Differential Multi-PAM Signals |
| 7307560 |
Phase Linearity Test Circuit |
| 7307461 |
System and Method for Adaptive Duty Cycle Optimization |
| 7302631 |
Low Overhead Coding Techniques |
| 7301831 |
Memory Systems With Variable Delays for Write Data Signals |
| 7298807 |
Circuit, Apparatus and Method for Adjusting a Duty-Cycle of a Clock Signal in Response to Incoming Serial Data |
| 7292637 |
Noise-Tolerant Signaling Schemes Supporting Simplified Timing and Data Recovery |
| 7292629 |
Selectable-Tap Equalizer |
| 7288973 |
Method and Apparatus for Fail-Safe Resynchronization With Minimum Latency |
| 7287119 |
Integrated Circuit Memory Device With Delayed Write Command Processing |
| 7287109 |
Method of Controlling a Memory Device Having a Memory Core |
| 7285443 |
Stacked Semiconductor Module |
| 7280428 |
Multi-Column Addressing Mode Memory System Including an Integrated Circuit Memory Device |
| 7275171 |
Method and Apparatus for Programmable Sampling Clock Edge Selection |
| 7274244 |
Pulse Multiplexed Output System |
| 7274242 |
Pass Transistors With Minimized Capacitive Loading |
| 7271623 |
Low-Power Receiver Equalization in a Clocked Sense Amplifier |
| 7269708 |
Memory Controller for Non-Homogeneous Memory System |
| 7269212 |
Low-Latency Equalization in Multi-Level, Multi-Line Communication Systems |
| 7268706 |
Low Power, DC-Balanced Serial Link Transmitter |
| 7268605 |
Technique for Operating a Delay Circuit |
| 7268602 |
Method and Apparatus for Accommodating Delay Variations Among Multiple Signals |
| 7266634 |
Configurable Width Buffered Module Having Flyby Elements |
| 7263149 |
Apparatus and Method for Generating a Distributed Clock Signal |
| 7257183 |
Digital Clock Recovery Circuit |
| 7254797 |
Input/Output Cells With Localized Clock Routing |
| 7254075 |
Integrated Circuit Memory System Having Dynamic Memory Bank Count and Page Size |
| 7248086 |
Leakage Compensation for Capacitors in Loop Filters |
| 7246274 |
Method and Apparatus for Estimating Random Jitter (RJ) and Deterministic Jitter (DJ) From Bit Error Rate (BER) |
| 7236894 |
Circuits, Systems and Methods for Dynamic Reference Voltage Calibration |
| 7233164 |
Offset Cancellation in a Multi-Level Signaling System |
| 7231306 |
Method and Apparatus for Calibrating Static Timing Offsets Across Multiple Outputs |
| 7225311 |
Memory Controller Device Having Timing Offset Capability |
| 7225292 |
Memory Module With Termination Component |
| 7222224 |
System and Method for Improving Performance in Computer Memory Systems Supporting Multiple Memory Access Latencies |
| 7222209 |
Expandable Slave Device System |
| 7219205 |
Memory Controller Device |
| 7216187 |
Memory System Including a Circuit to Convert Between Parallel and Serial Bits |
| 7215161 |
Wave Shaping Output Driver to Adjust Slew Rate and/or Pre-Emphasis of an Output Signal |
| 7213121 |
Memory Device Having Asynchronous/Synchronous Operating Modes |
| 7210016 |
Method, System and Memory Controller Utilizing Adjustable Write Data Delay Settings |
| 7210015 |
Memory Device Having at Least a First and a Second Operating Mode |
| 7209997 |
Controller Device and Method for Operating Same |
| 7209397 |
Memory Device With Clock Multiplier Circuit |
| 7206897 |
Memory Module Having an Integrated Circuit Buffer Device |
| 7206896 |
Integrated Circuit Buffer Device |
| 7200710 |
Buffer Device and Method of Operation in a Buffer Device |
| 7200055 |
Memory Module With Termination Component |
| 7199728 |
Communication System With Low Power, DC-Balanced Serial Link |
| 7199615 |
High Speed Signaling System With Adaptive Transmit Pre-Emphasis and Reflection Cancellation |
| 7199605 |
Method and Apparatus for Low Capacitance, High Output Impedance Driver |
| 7198197 |
Method and Apparatus for Data Acquisition |
| 7197684 |
Single-Ended Transmission for Direct Access Test Mode Within a Differential Input and Output Circuit |
| 7197611 |
Integrated Circuit Memory Device Having Write Latency Function |
| 7196567 |
Systems and Methods for Controlling Termination Resistance Values for a Plurality of Communication Channels |
| 7196539 |
Adaptive Signal Termination |
| 7194155 |
Adaptive Control for Mitigating Interference in a Multimode Transmission Medium |
| 7194056 |
Determining Phase Relationships Using Digital Phase Values |
| 7193467 |
Differential Amplifiers and Methods of Using Same |
| 7190754 |
Transceiver With Selectable Data Rate |
| 7187721 |
Transition-Time Control in a High-Speed Data Transmitter |
| 7187572 |
Early Read After Write Operation Memory Device, System and Method |
| 7184483 |
Technique for Emulating Differential Signaling |
| 7183805 |
Method and Apparatus for Multi-Mode Driver |
| 7180959 |
Technique for Utilizing Spare Bandwidth Resulting From the Use of a Code in a Multi-Level Signaling System |
| 7180958 |
Technique for Utilizing Spare Bandwidth Resulting From the Use of a Transistion-Limiting Code in a Multi-Level Signaling System |
| 7180957 |
Technique For Utilizing Spare Bandwidth Resulting From the Use of a Transition-Limiting Code in a Multi-Level Signaling System |
| 7,177,998 B2 |
Method, System and Memory Controller Utilizing Adjustable Read Data Delay Settings |
| 7,176,721 B2 |
Signal Receiver With Data Precessing Function |
| 7,174,400 B2 |
Integrated Circuit Device That Stores a Value Representative of an Equalization Co-Efficient Setting |
| 7,171,528 B2 |
Method and Apparatus for Generating a Write Mask Key |
| 7,171,321 B2 |
Individual Data Line Strobe-Offset Control in Memory Systems |
| 7,170,314 B2 |
Multiple Channel Modules and Bus Systems Using Same |
| 7,167,039 B2 |
Memory Device Having an Adjustable Voltage Swing Setting |
| 7,167,019 B2 |
Method and Device for Transmission With Reduced Crosstalk |
| 7,164,997 B2 |
Bus Line Current Calibration |
| 7,164,292 B2 |
Reducing Electrical Noise During Bus Turnaround in Signal Transfer Systems |
| 7,162,672 B2 |
Multilevel Signal Interface Testing With Binary Test Apparatus By Emulation of Multilevel Signals |
| 7,162,376 B2 |
Circuits, Systems and Methods for Dynamic Reference Voltage Calibration |
| 7,161,513 B2 |
Apparatus and Method for Improving Resolution of a Current Mode Driver |
| 7,161,400 B2 |
Phase Synchronization for Wide Area Integrated Circuits |
| 7,159,136 B2 |
Drift Tracking Feedback for Communication Channels |
| 7,158,536 B2 |
Adaptive-Allocation of I/O Bandwidth Using a Configurable Interconnect Topology |
| 7,154,302 B2 |
Method and Apparatus for Selectably Providing Single-Ended and Differential Signaling With Controllable Impedance and Transition Time |
| 7,151,390 B2 |
Calibration Methods and Circuits for Optimized On-Die Termination |
| 7,149,856 B2 |
Method and Apparatus for Adjusting the Performance of a Synchronous Memory System |
| 7,148,699 B1 |
Technique for Calibrating Electronic Devices |
| 7,142,612 B2 |
Method and Apparatus for Multi-Level Signaling |
| 7,142,475 B2 |
Memory Device Having a Configurable Oscillator for Refresh Operation |
| 7,138,877 B2 |
PLL and Method for Providing a Single/Multiple Adjustable Frequency Range |
| 7,137,048 B2 |
Method and Apparatus for Evaluating and Optimizing a Signaling System |
| 7,136,949 B2 |
Method and Apparatus for Position Dependent Data Scheduling |
| 7,136,310 B2 |
Programmable Output Driver Turn-on Time for an Integrated Circuit Memory Device |
| 7,135,925 B2 |
Adaptive Bias Scheme for High-Voltage Compliance in Serial Links |
| 7,135,903 B2 |
Phase Jumping Locked Loop Circuit |
| 7,134,101 B2 |
Active Impedance Compensation |
| 7,133,945 B2 |
Scalable I/O Signaling Topology Using Source-Calibrated Reference Voltages |
| 7,133,463 B1 |
Linear Transformation Circuits |
| 7,130,944 B2 |
Chip-to-Chip Communication System Using an AC-Coupled Bus and Devices Employed in Same |
| 7,129,739 B2 |
Method and Apparatus for Selectably Providing Single-Ended and Differential Signaling With Controllable Impedance and Transition Time |
| 7,127,017 B1 |
Clock Recovery Circuit With Second Order Digital Filter |
| 7,127,003 B2 |
Method and Apparatus for Communicating Information Using Different Signaling Types |
| 7,126,510 B2 |
Circuit Calibration System and Method |
| 7,126,435 B2 |
Voltage Controlled Oscillator Amplitude Control Circuit |
| 7,126,408 B2 |
Method and Apparatus for Receiving High-Speed Signals With Low Latency |
| 7,126,378 B2 |
High Speed Signaling System With Adaptive Transmit Pre-Emphasis |
| 7,124,270 B2 |
Transceiver With Latency Alignment Circuitry |
| 7,124,221 B1 |
Low Latency Multi-Level Communication Interface |
| 7,122,889 B2 |
Semiconductor Module |
| 7,119,549 B2 |
Output Calibrator With Dynamic Precision |
| 7,113,550 B2 |
Technique for Improving the Quality of Digital Signals in a Multi-Level Signaling System |
| 7,110,322 B2 |
Memory Module Including an Integrated Circuit Device |
| 7,102,390 B2 |
Method and Apparatus for Signal Reception Using Ground Termination and/or Non-Ground Termination |
| 7,099,786 B2 |
Signaling Accomodation |
| 7,099,424 B1 |
Clock Data Recovery With Selectable Phase Control |
| 7,099,404 B2 |
Digital Transmitter |
| 7,099,395 B1 |
Reducing Coupled Noise in Pseudo-Differential Signaling Systems |
| 7,095,789 B2 |
Communication Channel Calibration for Drift Conditions |
| 7,095,265 B2 |
PVT-Compensated Clock Distribution |
| 7,093,145 B2 |
Method and Apparatus for Calibrating a Multi-Level Current Mode Driver Having a Plurality of Source Calibration Signals |
| 7,092,472 B2 |
Data-Level Clock Recovery |
| 7,092,449 B2 |
High-Speed Communication System With a Feedback Synchronization Loop |
| 7,091,761 B2 |
Impedance Controlled Output Driver |
| 7,089,442 B2 |
Fault-Tolerant Clock Generator |
| 7,088,270 B1 |
Low Power, DC-Balanced Serial Link |
| 7,088,127 B2 |
Adaptive Impedance Output Driver Circuit |
| 7,085,906 B2 |
Memory Device |
| 7,085,872 B2 |
High Frequency Bus System |
| 7,084,681 B2 |
PLL Lock Detection Circuit Using Edge Detection and a State Machine |
| 7,081,782 B2 |
Locked Loop With Dual Rail Regulation |
| 7,078,979 B2 |
Phase Controlled Oscillator Circuit With Input Signal Coupler |
| 7,078,790 B2 |
Semiconductor Stacked Die Devices and Methods of Forming Semiconductor Stacked Die Devices |
| 7,076,377 B2 |
Circuit, Apparatus and Method for Capturing a Representation of a Waveform From a Clock-Data Recovery (CDR) Unit |
| 7,073,035 B2 |
Techniques for Increasing Bandwidth in Port-Per-Module Memory Systems Having Mismatched Memory Modules |
| 7,072,415 B2 |
Method and Apparatus for Generating Multi-Level Reference Voltage in Systems Using Equalization or Crosstalk Cancellation |
| 7,072,355 B2 |
Periodic Interface Calibration for High Speed Communication |
| 7,065,622 B2 |
Transceiver With Latency Alignment Circuitry |
| 7,064,602 B2 |
Dynamic Gain Compensation and Calibration |
| 7,062,597 B2 |
Integrated Circuit Buffer Device |
| 7,061,406 B1 |
Low Power, DC-Balanced Serial Link Transmitter |
| 7,061,273 B2 |
Method and Apparatus for Multi-Mode Driver |
| 7,057,460 B2 |
Differential Amplifier With Adaptive Biasing and Offset Cancellation |
| 7,054,771 B2 |
Bus Line Current Calibration |
| 7,051,151 B2 |
Integrated Circuit Buffer Device |
| 7,051,130 B1 |
Integrated Circuit Device That Stores a Value Representative of a Drive Strength Setting |
| 7,051,129 B2 |
Memory Device Having a Programmable Drive Strength Setting |
| 7,047,375 B2 |
Memory System and Method for Two Step Memory Write Operations |
| 7,046,078 B2 |
Method and Apparatus for Distributed Voltage Compensation With a Voltage Driver That is Responsive to Feedback |
| 7,046,056 B2 |
System With Dual Rail Regulated Locked Loop |
| 7,043,599 B1 |
Dynamic Memory Supporting Simultaneous Refresh and Data-Access Transactions |
| 7,042,914 B2 |
Calibrated Data Communication System and Method |
| 7,039,782 B2 |
Memory System With Channel Multiplexing of Multiple Memory Devices |
| 7,039,147 B2 |
Delay Locked Loop Circuitry for Clock Delay Adjustment |
| 7,039,118 B1 |
High-Speed Communication System With a Feedback Synchronization Loop |
| 7,038,543 B2 |
Collective Automatic Gain Control |
| 7,037,757 B2 |
Stacked Semiconductor Module |
| 7,032,058 B2 |
Apparatus and Method for Topography Dependent Signaling |
| 7,032,057 B2 |
Integrated Circuit With Transmit Phase Adjustment |
| 7,031,868 B2 |
Method and Apparatus for Performing Testing of Interconnections |
| 7,030,657 B2 |
High Speed Signaling System With Adaptive Transmit Pre-Emphasis and Reflection Cancellation |
| 7,027,307 B2 |
Clock Routing in Multiple Channel Modules and Bus Systems |
| 7,026,848 B2 |
Pre-Driver Circuit |
| 7,024,502 B2 |
Apparatus and Method for Topography Dependent Signaling |
| 7,017,002 B2 |
System Featuring a Master Device, a Buffer Device and a Plurality of Integrated Circuity Memory Devices |
| 7,015,721 B2 |
Push-Pull Output Driver |
| 7,012,812 B2 |
Memory Module |
| 7,012,330 B1 |
Integrated Circuit Device Having I/O Structures With Reduced Input Loss |
| 7,010,658 B2 |
Transceiver With Latency Alignment Circuitry |
| 7,010,642 B2 |
System Featuring a Controller Device and a Memory Module That Includes an Integrated Circuit Buffer Device and a Plurality of Integrated Circuit Memory Devices |
| 7,006,932 B1 |
Technique for Determining Performance Characteristics of Electronic Devices and Systems |
| 7,005,939 B2 |
Input/Output Circuit With On-Chip Inductor to Reduce Parasitic Capacitance |
| 7,003,639 B2 |
Memory Controller With Power Management Logic |
| 7,003,618 B2 |
System Featuring Memory Modules That Include an Integrated Circuit Buffer Devices |
| 7,002,500 B2 |
Circuit, Apparatus and Method for Improved Current Distribution of Output Drivers Enabling Improved Calibration Efficiency and Accuracy |
| 7,002,367 B2 |
Method and Apparatus for Low Capacitance, High Output Impedance Driver |
| 7,000,062 B2 |
System and Method Featuring a Controller Device and a Memory Module That Includes an Integrated Circuit Buffer Device and a Plurality of Integrated Circuit Memory Devices |
| 6,999,516 B1 |
Technique for Emulating Differential Signaling |
| 6,999,332 B2 |
Semiconductor Package With a Controlled Impedance Bus and Method of Forming Same |
| 6,998,892 B1 |
Method and Apparatus for Accommodating Delay Variations Among Multiple Signals |
| 6,998,889 B2 |
Circuit, Apparatus and Method for Obtaining a Lock State Value |
| 6,990,042 B2 |
Single-Clock, Strobeless Signaling System |
| 6,988,044 B2 |
Bus Line Current Calibration |
| 6,987,823 B1 |
System and Method for Aligning Internal Transmit and Receive Clocks |
| 6,982,922 B2 |
Single-Clock, Strobeless Signaling System |
| 6,982,587 B2 |
Equalizing Transceiver With Reduced Parasitic Capacitance |
| 6,980,020 B2 |
Calibration Methods and Circuits for Optimized On-Die Termination |
| 6,977,980 B2 |
Timing Synchronization Methods and Systems for Transmit Parallel Interfaces |
| 6,976,114 B1 |
Method and Apparatus for Simultaneous Bidirectional Signaling in a Bus Topology |
| 6,975,956 B2 |
Multiple Sweep Point Testing of Circuit Devices |
| 6,975,558 B2 |
Integrated Circuit Device |
| 6,975,160 B2 |
System Including an Integrated Circuit Memory Device Having an Adjustable Output Voltage Setting |
| 6,975,159 B2 |
Method of Operation in a System Having a Memory Device Having an Adjustable Output Voltage Setting |
| 6,968,024 B1 |
Apparatus and Method for Operating a Master-Slave System With a Clock Signal and a Separate Phase Signal |
| 6,967,514 B2 |
Method and Apparatus for Digital Duty Cycle Adjustment |
| 6,965,262 B2 |
Method and Apparatus for Receiving High Speed Signals With Low Latency |
| 6,963,956 B2 |
Apparatus and Method for Pipelined Memory Operations |
| 6,963,232 B2 |
Compensator for Leakage Through Loop Filter Capacitors in Phase-Locked Loops |
| 6,961,862 B2 |
Drift Tracking Feedback for Communication Channels |
| 6,961,831 B2 |
Techniques for Increasing Bandwidth in Port-Per-Module Memory Systems Having Mismatched Memory Modules |
| 6,960,952 B2 |
Configuring and Selecting a Duty Cycle for an Output Driver |
| 6,960,948 B2 |
System With Phase Jumping Locked Loop Circuit |
| 6,954,837 B2 |
Consolidation of Allocated Memory to Reduce Power Consumption |
| 6,954,095 B2 |
Apparatus and Method for Generating Clock Signals |
| 6,952,431 B1 |
Clock Multiplying Delay-Locked Loop for Data Communications |
| 6,952,123 B2 |
System With Dual Rail Regulated Locked Loop |
| 6,950,956 B2 |
Integrated Circuit With Timing Adjustment Mechanism and Method |
| 6,949,958 B2 |
Phase Comparator Capable of Tolerating a Non-50% Duty-Cycle Clocks |
| 6,937,073 B2 |
Frequency Multiplier With Phase Comparator |
| 6,934,201 B2 |
Asynchronous, High-Bandwidth Memory Component Using Calibrated Timing Elements |
| 6,931,467 B2 |
Memory Integrated Circuit Device Which Samples Data Upon Detection of a Strobe Signal |
| 6,928,128 B1 |
Clock Alignment Circuit Having a Self Regulating Voltage Supply |
| 6,924,660 B2 |
Calibration Methods and Circuits for Optimized On-Die Termination |
| 6,922,092 B2 |
Impedance Controlled Output Driver |
| 6,922,091 B2 |
Locked Loop Circuit With Clock Hold Function |
| 6,920,540 B2 |
Timing Calibration Apparatus and Method for a Memory Device Signaling System |
| 6,920,402 B1 |
Technique for Determining Performance Characteristics of Electronic Devices and Systems |
| 6,919,749 B2 |
Apparatus and Mehtod for a Digital Delay Locked Loop |
| 6,917,312 B2 |
Technique for Improving the Quality of Digital Signals in a Multi-Level Signaling System |
| 6,912,620 B2 |
Memory Device Which Receives Write Masking Information |
| 6,911,853 B2 |
Locked Loop With Dual Rail Regulation |
| 6,909,387 B2 |
Circuit, Apparatus and Method for Improved Current Distribution of Output Drivers Enabling Improved Calibration Efficiency and Accuracy |
| 6,902,953 B2 |
Methods of Forming Semiconductor Stacked Die Devices |
| 6,898,085 B2 |
Multiple Channel Modules and Bus Systems Using Same |
| 6,897,713 B1 |
Method and Apparatus for Distributed Voltage Compensation With a Voltage Driver That is Responsive to Feedback |
| 6,897,699 B1 |
Clock Distribution Network With Process, Supply-Voltage, and Temperature Compensation |
| 6,889,304 B2 |
Memory Device Supporting a Dynamically Configurable Core Organization |
| 6,889,300 B2 |
Memory System and Method for Two Step Write Operations |
| 6,882,593 B2 |
Adjustable Clock Driver Circuit |
| 6,879,195 B2 |
PLL Lock Detection Circuit Using Edge Detection |
| 6,877,054 B2 |
Method and Apparatus for Position Dependent Data Scheduling |
| 6,876,248 B2 |
Signaling Accomodation |
| 6,873,939 B1 |
Method and Apparatus for Evaluating and Calibrating a Signaling System |
| 6,870,419 B1 |
Memory System Including a Memory Device Having a Controlled Output Driver Characteristic |
| 6,870,246 B1 |
Method and Apparatus for Providing an Integrated Circuit Cover |
| 6,868,474 B2 |
High Performance Cost Optimized Memory |
| 6,864,896 B2 |
Scalable Unified Memory Architecture |
| 6,861,916 B2 |
Phase Controlled Oscillator Circuit With Input Signal Coupler |
| 6,861,884 B1 |
Phase Synchronization for Wide Area Integrated Circuits |
| 6,856,169 B2 |
Method and Apparatus for Signal Reception Using Ground Termination and/or Non-Ground Termination |
| 6,854,030 B2 |
Integrated Circuit Device Having a Capacitive Coupling Element |
| 6,853,557 B1 |
Multi-Channel Memory Architecture |
| 6,842,864 B1 |
Method and Apparatus for Configuring Access Times of Memory Devices |
| 6,839,393 B1 |
Apparatus and Method for Controlling a Master/Slave System Via Master Device Synchronization |
| 6,839,266 B1 |
Memory Module With Offset Data Lines and Bit Line Swizzle Configuration |
| 6,836,521 B2 |
Apparatus and Method for Generating a Distributed Clock Signal Using Gear Ratio Techniques |
| 6,836,503 B2 |
Apparatus for Data Recovery in a Synchronous Chip-to-Chip System |
| 6,833,984 B1 |
Semiconductor Module With Serial Bus Connection to Multiple Dies |
| 6,826,663 B2 |
Coded Write Masking |
| 6,826,657 B1 |
Techniques for Increasing Bandwidth in Port-Per-Module Memory Systems Having Mismatched Memory Modules |
| 6,825,841 B2 |
Granularity Memory Column Access |
| 6,819,137 B1 |
Technique for Voltage Level Shifting in Input Circuitry |
| 6,813,722 B1 |
Programmable Timing Module |
| 6,812,736 B2 |
Method and Apparatus for Selectably Providing Single-Ended and Differential Signaling With Controllable Impedance and Transition Time |
| 6,810,449 B1 |
Protocol for Communication With Dynamic Memory |
| 6,809,600 B2 |
Dual Loop Phase Lock Loops Using Dual Voltage Supply Regulators |
| 6,809,569 B2 |
Circuit, Apparatus and Method Having a Cross-Coupled Load With Current Mirrors |
| 6,807,598 B2 |
Integrated Circuit Device Having Double Data Rate Capability |
| 6,806,728 B2 |
Circuit and Method for Interfacing to a Bus Channel |
| 6,803,823 B2 |
Circuit, Apparatus and Method for an Adaptive Voltage Swing Limiter |
| 6,801,099 B2 |
Methods for Bi-Directional Signaling |
| 6,798,243 B1 |
Apparatus and Method for Level-Shifting Input Receiver Circuit From High External Voltage to Low Internal Supply Voltage |
| 6,788,594 B2 |
Asynchronous, High-Bandwidth Memory Component Using Calibrated Timing Elements |
| 6,788,593 B2 |
Asynchronous, High-Bandwidth Memory Component Using Calibrated Timing Elements |
| 6,785,782 B1 |
Techniques for Increasing Bandwidth in Port-Per-Module Memory Systems Having Mismatched Memory Modules |
| 6,782,460 B2 |
Pipelined Memory Controller and Method of Controlling Access to Memory Devices in a Memory System |
| 6,782,459 B1 |
Method and Apparatus for Controlling a Read Valid Window of a Synchronous Memory Device |
| 6,781,416 B1 |
Push-Pull Output Driver |
| 6,781,405 B2 |
Adaptive Signal Termination |
| 6,778,458 B2 |
DRAM Core Refresh With Reduced Spike Current |
| 6,775,809 B1 |
Technique for Determining Performance Characteristics of Electronic Systems |
| 6,775,328 B1 |
High-Speed Communication System With a Feedback Synchronization Loop |
| 6,772,351 B1 |
Method and Apparatus for Calibrating a Multi-Level Current Mode Driver |
| 6,772,315 B1 |
Translation Lookaside Buffer Extended to Provide Physical and Main-Memory Addresses |
| 6,769,050 B1 |
Techniques for Increasing Bandwidth in Port-Per-Module Memory Systems Having Mismatched Memory Modules |
| 6,765,800 B2 |
Multiple Channel Modules and Bus Systems Using Same |
| 6,760,857 B1 |
System Having Both Externally and Internally Generated Clock Signals Being Asserted on the Same Clock Pin in Normal and Test Modes of Operation Respectively |
| 6,759,881 B2 |
System With Phase Jumping Locked Loop Circuit |
| 6,757,789 B2 |
Apparatus and Method for Maximizing Information Transfers Over Limited Interconnect Resources |
| 6,754,783 B2 |
Memory Controller With Power Management Logic |
| 6,754,120 B1 |
DRAM Output Circuitry Supporting Sequential Data Capture to Reduce Core Access Times |
| 6,751,696 B2 |
Memory Device Having a Programmable Register |
| 6,742,097 B2 |
Consolidation of Allocated Memory to Reduce Power Consumption |
| 6,731,545 B2 |
Translating Data to Reduce Worst Case Power Consumption |
| 6,731,148 B2 |
Apparatus and Method for Generating Clock Signals |
| 6,728,819 B2 |
Synchronous Memory Device |
| 6,727,759 B2 |
Collective Automatic Gain Control |
| 6,721,226 B2 |
Methods and Systems for Reducing Heat Flux in Memory Systems |
| 6,721,189 B1 |
Memory Module |
| 6,720,643 B1 |
Stacked Semiconductor Module |
| 6,718,431 B2 |
Apparatus and Method for Pipelined Memory Operations |
| 6,715,020 B2 |
Synchronous Integrated Circuit Device |
| 6,714,431 B2 |
Semiconductor Package With a Controlled Impedance Bus and Method of Forming Same |
| 6,701,446 B2 |
Power Control System For Synchronous Memory Device |
| 6,697,295 B2 |
Memory Device Having a Programmable Register |
| 6,687,780 B1 |
Expandable Slave Device System |
| 6,684,285 B2 |
Synchronous Integrated Circuit Device |
| 6,684,263 B2 |
Apparatus and Method for Topography Dependent Signaling |
| 6,681,288 B2 |
Memory Device Which Receives Write Masking Information |
| 6,674,772 B1 |
Data Communications Circuit With Multi-Stage Multiplexing |
| 6,664,814 B1 |
Output Driver for an Integrated Circuit |
| 6,657,871 B2 |
Multiple Channel Modules and Bus System Using Same |
| 6,657,468 B1 |
Apparatus and Method for Controlling Edge Rates of Digital Signals |
| 6,643,787 B1 |
Bus System Optimization |
| 6,643,752 B1 |
Transceiver With Latency Alignment Circuitry |
| 6,617,936 B2 |
Phase Controlled Oscillator |
| 6,608,507 B2 |
Memory System Including a Memory Device Having a Controlled Output Driver Characteristic |
| 6,600,374 B2 |
Collective Automatic Gain Control |
| 6,598,171 B1 |
Integrated Circuit I/O Using a High Performance Bus Interface |
| 6,597,616 B2 |
DRAM Core Refresh With Reduced Spike Current |
| 6,590,781 B2 |
Clock Routing in Multiple Channel Modules and Bus Systems |
| 6,589,059 B2 |
Chip Socket Assembly and Chip File Assembly for Semiconductor Chips |
| 6,584,037 B2 |
Memory Device Which Samples Data After an Amount of Time Transpires |
| 6,573,779 B2 |
Duty Cycle Integrator With Tracking Common Mode Feedback Control |
| 6,571,325 B1 |
Pipelined Memory Controller and Method of Controlling Access to Memory Devices in a Memory System |
| 6,570,814 B2 |
Integrated Circuit Device Which Outputs Data After a Latency Period Transpires |
| 6,564,281 B2 |
Synchronous Memory Device Having Automatic Precharge |
| 6,556,052 B2 |
Semiconductor Controller Device Having a Controlled Output Driver Characteristic |
| 6,553,452 B2 |
Synchronous Memory Device Having a Temperature Register |
| 6,546,446 B2 |
Synchronous Memory Device Having Automatic Precharge |
| 6,542,976 B2 |
Memory Device Having an Internal Register |
| 6,542,555 B2 |
Digital Transmitter With Equalization |
| 6,542,416 B1 |
Methods and Arrangements for Conditionally Enforcing CAS Latencies in Memory Devices |
| 6,538,336 B1 |
Wirebond Assembly for High-Speed Integrated Circuits |
| 6,532,522 B1 |
Asynchronous Request/Synchronous Data Dynamic Random Access Memory |
| 6,522,199 B2 |
Reconfigurable Dual-Mode Multiple Stage Operational Amplifiers |
| 6,513,103 B1 |
Method and Apparatus for Adjusting the Performance of a Synchronous Memory System |
| 6,513,081 B2 |
Memory Device Which Receives an External Reference Voltage Signal |
| 6,509,756 B1 |
Method and Apparatus for Low Capacitance, High Output Impedance Driver |
| 6,504,875 B2 |
Apparatus for Multilevel Signaling |
| 6,504,438 B1 |
Dual Loop Phase Lock Loops Using Dual Voltage Supply Regulators |
| 6,504,405 B1 |
Differential Amplifier With Selectable Hysteresis and Buffered Filter |
| 6,502,161 B1 |
Memory System Including a Point-to-Point Linked MemorySubsystem |
| 6,496,897 B2 |
Semiconductor Memory Device Which Receives Write Masking Information |
| 6,496,889 B1 |
Chip-To-Chip Communication System Using an AC-Coupled Bus and Devices Employed in Same |
| 6,493,789 B2 |
Memory Device Which Receives Write Masking and Automatic Precharge Information |
| 6,480,035 B1 |
Phase Detector With Minimized Phase Detection Error |
| 6,476,656 B2 |
Low-Power Low-Jitter Variable Delay Timing Circuit |
| 6,470,405 B2 |
Protocol for Communication With Dynamic Memory |
| 6,469,555 B1 |
Apparatus and Method for Generating Multiple Clock Signals From a Single Loop Circuit |
| 6,462,591 B2 |
Semiconductor Memory Device Having a Controlled Output Driver Characteristic |
| 6,452,863 B2 |
Method of Operating a Memory Device Having a Variable Data Input Length |
| 6,449,159 B1 |
Semiconductor Module With Imbedded Heat Spreader |
| 6,426,984 B1 |
Apparatus and Method for Reducing Clock Signal Phase Skew in a Master-Slave System With Multiple Latent Clock Cycles |
| 6,426,916 B2 |
Memory Device Having a Variable Data Output Length and a Programmable Register |
| 6,415,339 B1 |
Memory Device Having a Plurality of Programmable Internal Registers And a Delay Time Register |
| 6,405,296 B1 |
Asynchronous Request/Synchronous Data Dynamic Random Access Memory |
| 6,396,887 B1 |
Apparatus and Method for Generating a Distributed Clock Signal Using Gear Ratio Techniques |
| 6,384,637 B1 |
Differential Amplifier With Selectable Hysteresis and Buffered Filter |
| 6,378,020 B2 |
System Having Double Data Transfer Rate and Integrated Circuit Therefor |
| 6,378,018 B1 |
Memory Device and System Including a Low Power Interface |
| 6,377,091 B1 |
Mechanism for Maintaining Relatively Constant Gain in a Multi-Component Apparatus |
| 6,373,768 B2 |
Apparatus and Method for Thermal Regulation in Memory Subsystems |
| 6,369,652 B1 |
Differential Amplifiers With Current and Resistance Compensation Elements for Balanced Output |
| 6,369,626 B1 |
Low Pass Filter for a Delay Locked Loop Circuit |
| 6,359,931 B1 |
Apparatus and Method for Multilevel Signaling |
| 6,356,975 B1 |
Apparatus and Method for Pipelined Memory Operations |
| 6,352,435 B1 |
Chip Socket Assembly and Chip File Assembly for Semiconductor Chips |
| 6,347,354 B1 |
Apparatus and Method for Maximizing Information Transfers Over Limited Interconnect Resources |
| 6,345,009 B1 |
Apparatus and Method for Refreshing Subsets of Memory Devices in a Memory System |
| 6,343,042 B1 |
DRAM Core Refresh With Reduced Spike Current |
| 6,342,800 B1 |
Charge Compensation Control Circuit and Method for Use With Output Driver |
| 6,340,909 B1 |
Method and Apparatus for Phase Interpolation |
| 6,340,900 B1 |
Phase Detector With Minimized Phase Detection Error |
| 6,330,193 B1 |
Method and Apparatus for Low Capacitance, High Output Impedance Driver |
| 6,324,120 B2 |
Memory Device Having a Variable Data Output Length |
| 6,321,282 B1 |
Apparatus and Method for Topography Dependent Signaling |
| 6,316,987 B1 |
Low-Power Low-Jitter Variable Delay Timing Circuit |
| 6,314,051 B1 |
Memory Device Having Write Latency |
| 6,310,814 B1 |
DRAM Apparatus and Method for Performing Refresh Operations |
| 6,308,232 B1 |
Electronically Moveable Terminator and Method for Using Same in a Memory System |
| 6,304,937 B1 |
Method of Operation of a Memory Controller |
| 6,304,104 B1 |
Method and Apparatus for Reducing Worst Case Power |
| 6,294,934 B1 |
Current Control Technique |
| 6,287,132 B1 |
Connector with Staggered Contact Design |
| 6,275,072 B1 |
Combined Phase Comparator and Charge Pump Circuit |
| 6,273,759 B1 |
Multi-Slot Connector With Integrated Bus Providing Contact Between Adjacent Modules |
| 6,266,730 B1 |
High-Frequency Bus System |
| 6,266,379 B1 |
Digital Transmitter With Equalization |
| 6,266,292 B1 |
DRAM Core Refresh with Reduced Spike Current |
| 6,266,285 B1 |
Method of Operating a Memory Device Having Write Latency |
| 6,263,448 B1 |
Power Control System For Synchronous Memory Device |
| 6,260,097 B1 |
Method and Apparatus for Controlling a Synchronous Memory Device |
| 6,234,820 B1 |
A Method and Apparatus for Joining Printed Circuit Boards |
| 6,226,757 B1 |
Apparatus and Method for Bus Timing Compensation |
| 6,226,754 B1 |
Apparatus and Method for Device Timing Compensation |
| 6,209,071 B1 |
Asynchronous Request/Synchronous Data Dynamic Random Access Memory |
| 6,205,191 B1 |
Method and Apparatus for Synchronizing a Control Signal |
| 6,204,697 B1 |
Low-Latency Small-Swing Clocked Receiver |
| 6,198,307 B1 |
Output Driver Circuit With Well-Controlled Output Impedance |
| 6,185,644 B1 |
Memory System Including a Plurality of Memory Devices and a Transceiver Device |
| 6,182,184 B1 |
Method of Operating a Memory Device Having a Variable Data Input Length |
| 6,178,130 B1 |
Apparatus and Method for Refreshing Subsets of Memory Devices in a Memory System |
| 6,169,434 B1 |
Conversion Circuit With Duty Cycle Correction for Small Swing Signals, and Associated Method |
| 6,708,248 |
Memory System With Channel Multiplexing of Multiple Memory Devices |
| 6,704,891 |
Method for Verifying and Improving Run-Time of a Memory Test |
| 6,696,829 |
Self-Resetting Phase Locked Loop |
| 6,687,319 |
Spread Spectum Clocking of Digital Signals |
| 6,683,472 |
Method and Apparatus for Selectably Providing Single-Ended and Differential Signaling With Controllable Impedance and Transition Time |
| 6,681,338 |
Methods and Systems for Reducing Signal Skew Caused by Dielectric Material Variations |
| 6,675,272 |
Method and Aparatus for Coordinating Memory Operations Among Diversely-Located Memory Components |
| 6,674,377 |
Circuit, Apparatus and Method for Improved Current Distribution of Output Drivers and Enabling Improved Calibration Efficientcy and Accuracy |
| 6,674,161 |
Semiconductor Stacked Die and Methods of Forming Semiconductor Stacked Die Devices |
| 6,671,836 |
Method and Apparatus for Testing Memory |
| 6,661,268 |
Charge Compensation Control Circuit and Method for Use With Output Driver |
| 6,646,953 |
Single-Clock, Strobeless Signaling System |
| 6,643,790 |
Duty Cycle Correction Circuit With Frequency-Dependent Bias Generator |
| 6,642,760 |
Apparatus and Mehtod for a Digital Delay Locked Loop |
| 6,642,746 |
Phase Detector With Minimized Phase Detection Error |
| 6,640,292 |
System and Method for Controlling Retire Buffer Operation in a Memory System |
| 6,636,935 |
Techniques for Increasing Bandwidth in Port-Per-Module Memory Systems Having Mismatched Memory Modules |
| 6,636,098 |
Differential Integrator and Related Circuitry |
| 6,621,373 |
Apparatus and Method for Utilizing a Lossy Dielectric Substrate in a High Speed Digital System |
| 6,619,973 |
Chip Socket Assembly and Chip File Assembly for Semiconductor Chips |
| 6,618,786 |
Current-Mode Bus Line Driver Having Increased Output Impedance |
| 6,617,871 |
Methods and Apparatus for Bi-Directional Signaling |
| 6,606,675 |
Clock Synchronization in Systems With Multi-Channel High-Speed Bus Subsystems |
| 6,600,338 |
Apparatus and Method for Level-Shifting Input Receiver Circuit From High External Voltage to Low Internal Supply Voltage |
| 6,594,326 |
Method and Apparatus of Synchronizing a Control Signal |
| 6,591,353 |
Protocol for Communication With Dynamic Memory |
| 6,583,035 |
Semiconductor Package With a Controlled Impedance Bus and Method of Forming Same |
| 6,574,759 |
Method for Verifying and Improving Run-Time of a Memory Test |
| 6,574,153 |
Asynchronous, High-Bandwidth Memory Component Using Calibrated Timing Elements |
| 6,570,944 |
Apparatus for Data Recovery in a Synchronous Chip-to-Chip System |
| 6,552,948 |
Methods and Systems for Reducing Heat Flux in Memory Systems |
| 6,546,343 |
Bus Line Current Calibration |
| 6,545,875 |
Multiple Channel Modules and Bus System Using Same |
| 6,539,072 |
Delay Locked Loop Circuitry for Clock Delay Adjustment |
| 6,530,062 |
Active Impedance Compensation |
| 6,523,089 |
Memory Controller With Power Management Logic |
| 6,516,365 |
Apparatus and Method for Topography Dependent Signaling |
| 6,514,794 |
Redistributed Bond Pads in Stacked Integrated Circuit Die Package |
| 6,504,448 |
Apparatus and Method for Transmission Line Impedance Tuning Using Periodic Capacitive Stubs |
| 6,473,439 |
Method and Apparatus for Fail-Safe Resynchronization With Minimum Latency |
| 6,462,588 |
Asymmetry Control for an Output Driver |
| 6,453,401 |
Memory Controller With Timing Constraint Tracking and Checking Unit and Corresponding Method |
| 6,448,828 |
Apparatus and Method for Edge Based Duty Cycle Conversion |
| 6,448,813 |
Output Driver Circuit With Well-Controlled Output Impedance |
| 6,447,321 |
Integrated Circuit Package for Coupling to a Printed Circuit Board |
| 6,404,660 |
Semiconductor Package With a Controlled Impedance Bus and Method of Forming Same |
| 6,401,167 |
High Performance Cost Optimized Memory |
| 6,396,329 |
Method and Apparatus for Receiving High Speed Signals With Low Latency |
| 6,376,904 |
Redistributed Bond Pads in Stacked Integrated Circuit Die Package |
| 6,373,293 |
Self-Synchronized Multi-Sample Quadrature Phase Detector |
| 6,370,668 |
High Speed Memory System Capable of Selectively Operating in Non-Chip-Kill and Chip-Kill Modes |
| 6,349,050 |
Methods and Systems for Reducing Heat Flux in Memory Systems |
| 6,343,352 |
Method and Apparatus For Two Step Memory Write Operations |
| 6,323,706 |
Apparatus and Method for Edge Based Duty Cycle Conversion |
| 6,282,604 |
Memory Controller and Method for Memory Devices With Multiple Banks of Memory Cells |
| 6,266,737 |
Memory Apparatus for Providing Memory with Write Enable Information |
| 6,232,796 |
Apparatus and Method for Detecting Two Data Bits Per Clock Edge |
| 6,163,178 |
Impedance Controlled Output Driver |
| 6,160,716 |
Motherboard Having One-Between Trace Connections for Connectors |
| 6,154,821 |
Method and Apparatus for Initializing Dynamic Random Access Memory (DRAM) Devices by Levelizing a Read Domain |
| 6,151,239 |
Data Packet With Embedded Mask |
| 6,134,172 |
Apparatus for Sharing Sense Amplifiers Between Memory Banks |
| 6,133,773 |
Variable Delay Element |
| 6,128,696 |
Synchronous Memory Device Utilizing Request Protocol and Method of Operation of Same |
| 6,125,422 |
Dependent Bank Memory Controller Method and Apparatus |
| ,125,157 |
Delay Locked Loop Circuitry for Clock Delay Adjustment |
| 6,122,688 |
Protocol for Communication With Dynamic Memory |
| 6,122,208 |
Circuit and Method for Column Redundancy for High Bandwidth Memories |
| 6,122,189 |
Data Packet With Embedded Mask |
| 6,111,445 |
Phase Interpolator With Noise Immunity |
| 6,107,849 |
Automatically Compensated Charge Pump |
| 6,107,847 |
Zero Power Reset Circuit for Low Voltage CMOS Circuits |
| 6,101,152 |
Method of Operating a Synchronous Memory Device |
| 6,094,075 |
Current Control Technique |
| 6,085,284 |
Method of Operating a Memory Device Having a Variable Data Output Length and an Identification Register |
| 6,075,744 |
DRAM Core Refresh With Reduced Spike Current |
| 6,075,743 |
Method and Apparatus for Sharing Sense Amplifiers Between Memory Banks |
| 6,075,730 |
High Performance Cost Optimized Memory With Delayed Memory Writes |
| 6,070,222 |
Synchronous Memory Device Having Identification Register |
| 6,067,594 |
High Frequency Bus System |
| 6,067,592 |
System Having a Synchronous Memory Device |
| 6,058,033 |
Voltage to Current Converter With Minimal Noise Sensitivity |
| 6,049,846 |
Integrated Circuit Having Memory Which Synchronously Samples Information With Respect to External Clock Signals |
| 6,047,346 |
System for Adjusting Slew Rate on an Output of a Drive Circuit by Enabling a Plurality of Pre-Drivers and a Plurality of Output Drivers |
| 6,044,426 |
Meomory System Having Memory Devices Each Including a Programmable Internal Register |
| 6,038,195 |
Synchronous Memory Device Having a Delay Time Register and Method of Operating Same |
| 6,035,369 |
Method and Apparatus for Providing a Memory With Write Enable Information |
| 6,035,365 |
Dual Clocked Synchronous Memory Device Having a Delay Time Register and Method of Operating Same |
| 6,034,918 |
Method of Operating a Memory Having a Variable Data Output Length and a Programmable Register |
| 6,032,215 |
Synchronous Memory Device Utilizing Two External Clocks |
| 6,032,214 |
Method of Operating a Synchronous Memory Device Having a Variable Data Output Length |
| 6,021,076 |
Apparatus and Method for Thermal Regulation in Memory Subsystems |
| 6,014,042 |
Phase Detector Using Switched Capacitors |
| 6,009,487 |
Method and Apparatus for Setting a Current of an Output Driver for the High Speed Bus |
| 6,007,357 |
Chip Socket Assembly and Chip File Assembly for Semiconductor Chips |
| 6,005,895 |
Apparatus and Method for Multilevel Signaling |
| 6,002,589 |
Integrated Circuit Package for Coupling to a Printed Circuit Board |
| 5,995,443 |
Synchronous Memory Device |
| 5,995,016 |
Method and Apparatus For N Choose M Device Selection |
| 5,983,320 |
Method and Apparatus for Externally Configuring and Modifying the Transaction Request Response Characteristics of a Semiconductor Device Coupled to a Bus |
| 5,977,798 |
Low-Latency Small-Swing Clocked Receiver |
| 5,966,731 |
Protocol for Communication With Dynamic Memory |
| 5,959,481 |
Bus Driver Circuit Including a Slew Rate Indicator Circuit Having a One Shot Circuit |
| 5,956,284 |
Method and Apparatus for Writing To Memory Components |
| 5,954,804 |
Synchronous Memory Device Having an Internal Register |
| 5,953,263 |
Synchronous Memory Device Having a Programmable Register and Method of Contolling Same |
| 5,945,862 |
Circuitry for the Delay Adjustment of a Clock Signal |
| 5,940,340 |
Method and Apparatus for Writing to Memory Components |
| 5,928,343 |
Memory Module Having Memory Devices Containing Internal Device ID Registers and Method of Initializing Same |
| 5,915,105 |
Integrated Circuit I/O Using a High Performance Bus Interface |
| 5,913,046 |
Protocol for Communication With Dynamic Memory |
| 5,908,333 |
Connector With Integral Transmission Line Bus |
| 5,896,545 |
Transmitting Memory Requests for Multiple Block Format Memory Operations the Requests Comprising Count Information, a Mask, and a Second Mask |
| 5,872,996 |
Method and Apparatus for Transmitting Memory Requests by Transmitting Portions of Count Data in Adjacent Words of a Packet |
| 5,844,913 |
Current Mode Interface Circuitry for an IC Test Device |
| 5,844,855 |
Method and Apparatus for Writing to Memory Components |
| 5,841,715 |
Integrated Circuit I/O Using High Performance Bus Interface |
| 5,841,580 |
Intergrated Circuit I/O Using a High Performance Bus Interface |
| 5,825,209 |
Circuitry for On-Off Delay Minimization and for Equalization for Phase Detector |
| 5,809,263 |
Integrated Circuit I/O Using a High Performance Bus Interface |
| 5,764,963 |
Method and Apparatus for Performing Maskable Multiple Color Block Writes |
| 5,748,914 |
Protocol for Communication With Dynamic Memory |
| 5,736,892 |
Differential Charge Pump Circuit With High Differential Impedance and Low Common Mode Impedance |
| 5,715,407 |
Process and Apparatus for Collision Detection on a Parallel Bus by Monitoring a First Line of the Bus During Even Bus Cycles for Indication of Overlapping Packets |
| 5,680,361 |
Method and Apparatus for Writing to Memory Components |
| 5,663,661 |
Modular Bus With Single or Double Parallel Termination |
| 5,657,481 |
Memory Device With Phase Locked Loop Circuitry |
| 5,638,334 |
Integrated Circuit I/O Using a High Performance Bus Interface |
| 5,614,855 |
Delay-Locked Loop |
| 5,578,940 |
Modular Bus With Single or Double Parallel Termination |
| 5,572,158 |
Amplifier With Active Duty Cycle Correction |
| 5,554,945 |
Voltage Controlled Phase Shifter With Unlimited Range |
| 5,537,573 |
Cache System and Method for Prefetching of Data |
| 5,513,327 |
Integrated Circuit I/O Using a High Performance Bus Interface |
| 5,511,024 |
Dynamic Random Access Memory System |
| 5,499,385 |
Method For Accessing and Transmitting Data To/From a Memory in Packets |
| 5,499,355 |
Prefetching Into a Cache to Minimize Main Memory Access Time and Cache Size in a Computer System |
| 5,488,321 |
Static High Speed Comparator |
| 5,485,490 |
Method and Circuitry For Clock Synchronization |
| 5,473,575 |
Integrated Circuit I/O Using a High Performance Bus Interface |
| 5,451,898 |
Bias Circuit and Differential Amplifier Having Stabilized Output Swing |
| 5,446,696 |
Method and Apparatus for Implementing Refresh in a Synchronous DRAM System |
| 5,434,817 |
Dynamic Random Access Memory System |
| 5,432,823 |
Method and Circuitry For Minimizing Clock-Data Skew in a Bus System |
| 5,430,676 |
Dynamic Random Access Memory System |
| 5,408,129 |
Integrated Circuit I/O Using a High Performance Bus Interface |
| 5,390,308 |
Method and Apparatus For Address Mapping of Dynamic Random Access Memory |
| 5,357,195 |
Testing Setup and Hold Input Timing Parameters of High Speed Integrated Circuit Devices |
| 5,355,391 |
High Speed Bus System |
| 5,337,285 |
Method and Apparatus for Power Control In Devices |
| 5,325,053 |
Apparatus for Testing Timing Parameters of High Speed Integrated Circuit Devices |
| 5,319,755 |
Integrated Circuit I/O Using High Performance Bus Interface |
| 5,268,639 |
Testing Timing Parameters of High Speed Integrated Circuit Devices |
| 5,254,883 |
Electrical Current Source Circuitry for a Bus |
| RE39,153 E |
Connector With Integral Transmission Line Bus |
| RE38,482 |
Delay Stage Circuitry for a Ring Oscillator |
| RE37,452 E |
At Frequency Phase Shifting Circuit for Use in a Quadratrue Clock Generator |
| RE37,409 E |
Memory and Method for Sensing Sub-Groups of Memory Elements |
| RE36,781 |
Differential Comparator for Amplifying Small Swing Signals to a Full Swing Output |
| RE36,013 |
Differential Charge Pump Circuit With High Differential and Low Common Mode Impedance |
|
Interested in licensing Rambus technology?
Communiqués de presse correspondants
|
